1. Field of the Invention
The present invention is related to circuit design and synthesis, and in particular, to techniques that preserve intelligibility by retaining abstraction while instantiating hardware description language (HDL) into a design.
2. Description of Related Art
When designing and implementing digital circuits in HDL, e.g., in such circuit representation languages as VHSIC (Very High Speed Integrated Circuit) Hardware Description Language (VHDL) or VERILOG (a trademark of Gateway Design Automation Corporation), when sequential logic is instantiated at circuit synthesis, the links between the abstract source HDL and the resulting synthesized circuit is difficult or impossible to comprehend.
In many designs, individual modules may be managed by different designers or groups, and are generally updated or redesigned in different phases and possibly in different steppings. In particular, design-for-test (DFT) functionality requires logic that is added to a design that may or may not play a role in operation of the digital circuit, but is provided for testing of the design and/or the individual devices. Integration of DFT with functional logic is one example of a design process in which independence of module redesign/replacement is desirable. Further, the DFT may not be easily implemented with high level abstract representations, since the clock sources may be different and DFT circuits typically include such features as clock gating and power management circuits. Further, if the DFT circuits are synthesized with the functional logic, the resulting synthesized circuit cannot be easily mapped to the input HDL so that the functional logic and the DFT logic are separately recognizable.
Solutions to the above-described integration problem have included hard-coding the DFT circuits in the HDL, but such implementations are limited to a particular subset of the HDL, since, as noted above, flip-flops in circuit blocks such as scan chains must be instantiated and not inferred, since their clock source is not the same as for state machines implemented in the functional logic blocks. In this solution, a change made to the particular implementation of the DFT circuits requires a rewrite of the HDL, since the DFT design is hard-coded. Another solution has been to insert the DFT functionality at synthesis time, which, while preserving the independents of the DFT circuits, eliminates the ability to verify the DFT design at register transfer level (RTL), as the HDL does not contain the DFT circuits.
Therefore, an alternative circuit design and synthesis technique is desired.